The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in\nXilinx SRAM-based Field ProgrammableGate Arrays (FPGAs).We developed a new high speed ICAP controller, named AC ICAP,\ncompletely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and\nframes, AC ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last\ncharacteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution\nto provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were\nimplemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI\ninterfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage\nof the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that\nrun-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5
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